Analog-to-Digital Converters (ADCs) are commonly used components in electronic systems. As they contain complex analog circuits, their design, implementation, and fabrication are difficult, time-consuming, and costly.
Integration of analog circuitry presents several issues that are not present when integrating digital circuits. Analog circuitry typically requires longer design cycles. Analog circuitry also lacks accurate models to detect failure and reduced performance often necessitating costly chip re-spins. In addition, the layout of analog circuits strongly affects the circuits' performance. Process changes also require redesign of the analog circuits. The performance of analog circuits is susceptible to temperature changes and is affected by component precision. Analog circuits are not suitable for applications which require very low supply voltages. Radiation hardening is difficult, lengthy and expensive. Finally, testability of analog circuits is more complicated.
Most ADCs can be classified into two groups based on the sampling frequency: Nyquist rate and oversampling converters. Nyquist rate converters sample the analog signals at a rate equal to twice the signal bandwidth, while oversampling converters use a much higher sampling frequency to convert the same signal. Single slope integrating, dual slope integrating, successive approximation, and flash converters are examples of Nyquist converters, while Delta and Sigma-Delta converters are examples of oversampling converters. Although Nyquist ADCs can achieve much higher conversion speeds than oversampling converters, their resolution heavily depends on the precision of their components. In fact often they require precise component matching or laser trimming which increases the manufacturing cost. On the contrary Sigma-Delta ADCs can relatively easily achieve very high resolutions while using low-cost CMOS processes. Moreover oversampling ADCs require only simple external analog anti-aliasing filters, because most of the anti-aliasing filtering is performed internally in the digital domain.
The basic Delta modulation systems were developed in the mid 1940's to encode analog signals such as speech into binary signals and to decode them. The modulators were based on 1st and 2nd order analog tracking loops which were successively improved with the addition of adaptive algorithms for the quantizer step size. Since there were already some stability issues with 2nd order systems due to the analog loop filter implementation, no attempt was made to increase the order of the tracking loops to improve their performance. Further developments were done only in the digital domain: adaptive digital Delta modulators were designed with the specific goal to encode and compress speech signals, while the task of digitizing the incoming analog speech signals was performed by traditional ADCs.
The functional structure of a Delta modulation system for speech coding applications is shown in FIG. 1A. The Delta modulator 100 produces a binary representation d(t) 102 of the analog input signal x(t) 104, which is transmitted over a channel. The decoder 120, shown in FIG. 1B recovers the transmitted analog signal x(t) 104 by filtering the received binary pulses d(t) 102 with the same filter 106 used in the feedback loop of the encoder. The clock frequency is much higher than the Nyquist rate. When the modulator 100 is tracking correctly, the input estimate y(t) 108 differs from the analog input signal x(t) 104 at any sampling instant by an amount which is less than the step size D. This situation is depicted in FIG. 2 for a 1st order Delta modulator with a pure integrator in the feedback loop. In the example of FIG. 1A, the sample & hold circuit 110 is assumed to hold the signal for a very small fraction of the sampling interval T 112 (shown in FIG. 2), thus generating very short binary pulses d(t) 102. When the binary pulses d(t) 102 are integrated by the integrator, the resulting input estimate waveform y(t) 108 consists of steps 114 with amplitude ±D and duration T, which oscillate about the analog input signal x(t) 104. A 2nd order modulator can track the input with a better approximation. Instead of a step signal, it produces a signal with ramps which tracks the analog signal x(t) 104 with a smaller error.
FIG. 3 shows a 1st order Delta modulator 130 used to convert the analog input signal x(t) 104 into the digital domain. The loop filter 106 is implemented with an external RC circuit. A decimator 132 downsamples the 1-bit signal to a lower rate (greater or equal to twice the signal bandwidth) and produces a multi-bit digital representation 133 of analog input signal x(t) 104. A flip-flop 134 and the decimator 132 are implemented in a Field-Programmable Gate Array (FPGA) 136. Also, a differential input of the FPGA 136 is used as a comparator 138. Any integrated circuit could be used instead of the FPGA.
Generally, Delta modulators have some issues: performance dependency on both amplitude and frequency of the input signal, stability problems with 2nd order loops, and oversampling frequencies too high to achieve adequate resolutions for more general purpose applications than voice devices. Due to these limitations, they were rarely used as ADCs except for some speech signal applications with low quality requirements.
It was the Sigma-Delta modulators developed in the early 1960's that, by addressing most of the limitations of the Delta modulators, became the technology of choice for ADCs in the audio signal range and later for higher frequency ranges. At the same time digital Sigma-Delta modulators, being fully digital and technology independent, quickly replaced traditional Digital-to-Analog converters (DACs) in similar applications.
Conventional Sigma-Delta modulators are mainly used to realize high-resolution, but, at the same time, cost-effective ADCs and DACs for applications such as consumer and professional audio, communications systems, sensors, and precision measurement devices. Several topologies have been adopted to implement them (e.g., single-loop, multiple-loop, combinations of 1st order and 2nd order modulators, and so on), but the basic functional structure of conventional Sigma-Delta modulators for ADCs 140 and DACs 150 is shown in FIG. 4 and FIG. 5. The comparators 143 and 142 can be replaced with a multi-bit quantizer to improve performance. The filter A(s) 144 is implemented inside the chips with switched-capacitor technology or continuous-time circuits. Typically, the modulators of Sigma-Delta DACs, such as the one of FIG. 5, are fully digital.
Even though conventional Delta and Sigma-Delta ADCs present some advantages compared to Nyquist ADCs (e.g. they do not require precision analog components and sophisticated analog anti-aliasing filters), they still require complex analog circuits.
Therefore, it would be advantageous if an ADC were largely digital, thus reducing the problems encountered in the integration of traditional ADCs.
Embodiments of the invention provide an ADC which, utilizing the benefits provided by a Delta-Sigma-Delta configuration, can be easily integrated in the digital CMOS technology without requiring any special processing step.
These and other advantages of embodiments of the invention, as well as additional inventive features, will be apparent from the description of the invention provided herein. In the paragraphs below, the terms “Sigma-Delta modulator” and “Sigma-Delta DAC” are used interchangeably.